AFE-CIM: A Current-Domain Compute-In-Memory Macro for Analog-to-Feature Extraction
Author:
Affiliation:
1. Georgia Institute of Technology,Department of Electrical and Computer Engineering,Atlanta,GA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268706.pdf?arnumber=10268706
Reference9 articles.
1. A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators
2. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021
3. A 40nm 64kb 26.56TOPS/W 2.37Mb/ mm2 RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75 Use of Sensing Dynamic Range;spetalnick,2022
4. A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference
5. Broadband Beamforming via Linear Embedding;delude;arXiv preprint arXiv 2206 07143,2022
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1. Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. Measurement of Aging Effect on an Analog Computing-In-Memory Macro in 28nm CMOS;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
3. BeamCIM: A Compute-In-Memory based Broadband Beamforming Accelerator using Linear Embedding;2024 IEEE Radio and Wireless Symposium (RWS);2024-01-21
4. An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro With Adaptive Conversion Time and Computation Voltage;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
5. Energy-Efficient Sensor Platform using Reliable Analog-to-Feature Extraction;2023 IEEE SENSORS;2023-10-29
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