The formal verification of a pipelined double-precision IEEE floating-point multiplier
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Publisher
IEEE Comput. Soc. Press
Link
http://xplorestaging.ieee.org/ielx2/3472/10225/00479878.pdf?arnumber=479878
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Verification of Arithmetic and Datapath Circuits with Symbolic Simulation;Handbook of Computer Architecture;2022
2. Formal Verification of n-bit ALU Using Theorem Proving;Lecture Notes in Computer Science;2018
3. Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback;Electronic Proceedings in Theoretical Computer Science;2011-10-20
4. Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL;The Computer Journal;2009-04-10
5. Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2009
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