Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping-Reference-Cited by-同舟云学术

Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping

Published:2009 Issue:6 Volume:E92-A Page:1454-1463
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

ZANG Chengjie¹,KIMURA Shinji¹

Affiliation:

1. Graduate School of Information, Production and Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E92.A/6/E92.A_6_1454/_pdf

Reference22 articles.

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2. [2] C. Kern and M. Greenstreet, “Formal verification in hardware design: A survey, ” ACM Trans. Des. Autom. Electron. Syst., vol.4, pp.123-193, April 1999.

3. [3] H. Nakamura, T. Arai, and M. Fujita, “Formal verification of a pipelined processor with new memory hierarchy using a commercial model checker, ” Proc. IEEE PRDCf02 (Pacific Rim Dependable Computing), pp.321-324, Tsukuba, Dec. 2002.

4. [4] T. Schubert, “High level formal verification of next-generation microprocessors, ” Proc. 40th ACM/IEEE Design Automation Conference, pp.1-6, 2003.

5. [5] M. Aagaard and C. Seger, “The formal verification of a pipelined double-precision IEEE floating-point multiplier, ” Proc. IEEE International Conference on Computer-Aided Design, pp.7-10, Nov. 1995.