Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback

Author:

Seidel Peter-Michael1

Affiliation:

1. Advanced Micro Devices

Publisher

Open Publishing Association

Reference14 articles.

1. The formal verification of a pipelined double-precision IEEE floating-point multiplier;Mark D Aagaard,1995

2. Formal Verification of the VAMP Floating Point Unit;Christoph Berg,2001

3. Formal Verification of the Pentium 4 Floating-Point Multiplier;Roope Kaivola,2002

4. A Tool for simplifying files of ACL2 definitions;Matt Kaufmann,2003

5. Formal Verification of Floating-Point RTL at AMD Using the ACL2 Theorem Prover;Matt Kaufmann,2005

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