Verification of Arithmetic and Datapath Circuits with Symbolic Simulation

Author:

Kaivola Roope,O’Leary John

Publisher

Springer Nature Singapore

Reference66 articles.

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3. Aagaard MD, Jones RB, Seger C-JH (1999b) Lifted-FL: a pragmatic implementation of combined model checking and theorem proving. In: Theorem proving in higher order logics. Springer, pp 323–340

4. Aagaard MD, Melham TF, O’Leary JW (1999c) Xs are for trajectory evaluation, Booleans are for theorem proving. In: Pierre L, Kropf T (eds) Correct hardware design and verification methods. Springer, pp 202–218

5. Aagaard MD, Jones RB, Kaivola R, Kohatsu KR, Seger C-JH (2000) Formal verification of iterative algorithms in microprocessors. In: Proceedings of the 37th annual design automation conference, pp 201–206

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