Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Author:

Roshan Weerasekera ,Li-Rong Zheng ,Dinesh Pamunuwa ,Hannu Tenhunen

Publisher

IEEE

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Power-aware partitioning and test time reduction for 3D-SoC;Innovations in Systems and Software Engineering;2022-09-06

2. Fast algorithms for test optimization of core based 3D SoC;Integration;2021-03

3. Clustered Fault Repairing Architecture for 3D ICs Using Redundant TSV;Proceedings of International Conference on Innovations in Software Architecture and Computational Systems;2021

4. Runtime Stress Estimation for Three-dimensional IC Reliability Management Using Artificial Neural Network;ACM Transactions on Design Automation of Electronic Systems;2019-11-14

5. Rentian scaling for the measurement of optimal embedding of complex networks into physical space;Journal of Complex Networks;2016-08-04

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