1. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
2. A single layer zero skew clock routing in X architecture;Science in China Series F: Information Sciences;2009-08
3. Robust Clock Tree Routing in the Presence of Process Variations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2008-08
4. Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building;2007 IEEE International Symposium on Circuits and Systems;2007-05
5. Reducing clock skew variability via crosslinks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2006-06