Reducing clock skew variability via crosslinks-Reference-Cited by-同舟云学术

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Reducing clock skew variability via crosslinks

Published:2006-06 Issue:6 Volume:25 Page:1176-1182
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Rajaram A.,Jiang Hu ,Mahapatra R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/34175/01629151.pdf?arnumber=1629151

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthesis and exploration of clock spines;IET Computers & Digital Techniques;2018-07-10

2. A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions;Proceedings of the 20th System Level Interconnect Prediction Workshop;2018-06-23

3. TSV-Based 3-D ICs: Design Methods and Tools;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-10

4. Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits;ETRI Journal;2014-12-01

5. Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation;ACM Transactions on Design Automation of Electronic Systems;2014-11-18

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