Synthesis and exploration of clock spines-Reference-Cited by-同舟云学术

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Synthesis and exploration of clock spines

Published:2018-07-10 Issue:5 Volume:12 Page:241-248
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Kim Youngchan¹,Kim Taewhan¹

Affiliation:

1. Department of Electrical and Computer EngineeringSeoul National UniversitySeoulRepublic of Korea

Funder

National Research Foundation of Korea

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2017.0234

Reference22 articles.

1. Synthesis of clock and power/ground networks

2. Edahiro M.: ‘A clustering‐based optimization algorithm in zero‐skew routings’.ACM/IEEE Design Automation Conf. Dallas TX USA 1993 pp.612–616

3. Kim T.Y. Kim T.: ‘Clock tree embedding for 3D ICs’.IEEE Asia and South Pacific Design Automation Conf. (ASP‐DAC) Taipei 2010 pp.486–491

4. Zero skew clock routing with minimum wirelength;Chao T.‐H.;IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,1992

5. A clock distribution network for microprocessors;Restle P.J.;IEEE J. Solid‐State Circuits,2001

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