Robust Clock Tree Routing in the Presence of Process Variations-Reference-Cited by-同舟云学术

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Robust Clock Tree Routing in the Presence of Process Variations

Published:2008-08 Issue:8 Volume:27 Page:1385-1397
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Padmanabhan U.,Wang J.M.,Hu J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/4567435/04527108.pdf?arnumber=4527108

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-07

3. Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis;Integration;2014-09

4. Integrated Resource Allocation and Binding in Clock Mesh Synthesis;ACM Transactions on Design Automation of Electronic Systems;2014-06

5. A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2012-08

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