High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing-Reference-Cited by-同舟云学术

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High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
language:
Short-container-title:

Author:

Hu Vita Pi-Ho¹,Liu Chang-Ju²,Chiang Hung-Li³,Wang Jer-Fu¹,Cheng Chao-Ching³,Chen Tzu-Chiang³,Chang Meng-Fan³

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University,Taipei,Taiwan

2. National Central University,Department of Electrical Engineering,Taoyuan,Taiwan

3. Corporate Research, Taiwan Semiconductor Manufacturing Company,Hsinchu,Taiwan

Funder

Ministry of Science and Technology in Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720511.pdf?arnumber=9720511

Reference10 articles.

1. Submicrometer-channel CMOS for low-temperature operation

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1. A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures;Solid-State Electronics;2024-04

3. Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures;Solid-State Electronics;2023-10

4. Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-08

5. Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02

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