Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper)
Author:
Affiliation:
1. Chair of AI Processor Design; Munich Institute of Robotics and Machine Intelligence, Technical University of Munich,Munich,Germany
2. Imec,Leuven,Belgium
3. University of Stuttgart,Semiconductor Test and Reliability,Stuttgart,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529386.pdf?arnumber=10529386
Reference37 articles.
1. Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors
2. Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits
3. A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
4. Systematical study of 14nm FinFET reliability: From device level stress to product HTOL
5. MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45nm and below
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