Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
Author:
Affiliation:
1. Imec,Leuven,Belgium,3001
2. KU Leuven,Leuven,Belgium,3001
3. Russian Academy of Sciences,A.F. Ioffe Physical-Technical Institute,Saint-Petersburg,Russia,194021
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764526.pdf?arnumber=9764526
Reference19 articles.
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4. Self-heating-aware CMOS reliability characterization using degradation maps
5. Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
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