Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs
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Published:2023-07-28
Issue:8
Volume:14
Page:1514
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
Tyaginov Stanislav1ORCID, O’Sullivan Barry1ORCID, Chasin Adrian1, Rawal Yaksh1, Chiarella Thomas1, de Carvalho Cavalcante Camila Toledo1, Kimura Yosuke1ORCID, Vandemaele Michiel1ORCID, Ritzenthaler Romain1, Mitard Jerome1, Palayam Senthil Vadakupudhu1ORCID, Reifsnider Jason1, Kaczer Ben1
Affiliation:
1. IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Abstract
We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference70 articles.
1. Auth, C., Allen, C., Blattner, A., Bergstrom, D., Brazier, M., Bost, M., Buehler, M., Chikarmane, V., Ghani, T., and Glassman, T. (2012, January 12–14). A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. Proceedings of the 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA. 2. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors;Ferain;Nature,2011 3. Barraud, S., Lapras, V., Previtali, B., Samson, M.P., Lacord, J., Martinie, S., Jaud, M.A., Athanasiou, S., Triozon, F., and Rozeau, O. (2017, January 2–6). Performance and design considerations for gate-all-around stacked-NanoWires FETs. Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 4. Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes;Nagy;IEEE Access,2020 5. Weckx, P., Ryckaert, J., Putcha, V., De Keersgieter, A., Boemmels, J., Schuddinck, P., Jang, D., Yakimets, D., Bardon, M.G., and Ragnarsson, L.Å. (2017, January 2–6). Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3 nm. Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA.
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