Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects-Reference-Cited by-同舟云学术

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Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Chasin Adrian,Bury Erik,Kaczer Ben,Franco Jacopo,Roussel Philippe,Ritzenthaler Romain,Mertens Hans,Horiguchi Naoto,Linten Dimitri,Mocuta Anda

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268343.pdf?arnumber=8268343

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