A 2.5D Heterogeneous Integration Demonstration for High Performance RF Application using High-Resistivity Through Si Interposer (TSI)-Reference-Cited by-同舟云学术

A 2.5D Heterogeneous Integration Demonstration for High Performance RF Application using High-Resistivity Through Si Interposer (TSI)

Published:2021-12-07 Issue: Volume: Page:
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Container-title:2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
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Author:

Loh Woon Leng,Guan Lim Teck,Chui K.-J.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9663571/9663865/09663901.pdf?arnumber=9663901

Reference4 articles.

1. Fine pitch Cu pillar wafer process development and seed layer etching characterization;siow;2012 IEEE 14th Electronics Packaging Technology Conference (EPTC),0

2. TSV Cu Filling Failure Modes and Mechanisms Causing the failures;woong;IEEE Trans Comp Packag Manufacturing Technol,0

3. A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via);woong;J Micromech Microeng,2013

4. RF MEMS Passives on High-Resistivity Silicon Substrates

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