Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogeneous Chiplet Integration-Reference-Cited by-同舟云学术

Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogeneous Chiplet Integration

Published:2022-12-07 Issue: Volume: Page:
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Container-title:2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)
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Author:

Wang Xiangyu¹,Rotaru Mihai Dragos¹,Haitao Yu¹,Chong Chai Tai¹,Chui King.-Jien¹

Affiliation:

1. Institute of Microelectronics (IME) A*STAR (Agency for Science Technology and Research),Singapore,138634

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10012686/10013085/10013241.pdf?arnumber=10013241

Reference5 articles.

1. Integration challenges of TSV backside via reveal process

2. A Novel Process to Reduce the Warpage of Bond Pair for Temporary Bonding and De-bonding Technique

3. A 2.5D Heterogeneous Integration Demonstration for High Performance RF Application using High-Resistivity Through Si Interposer (TSI)

4. Total cost effective scallop free Si etching for 2.5D & 3D TSV fabrication technologies in 300mm wafer

5. A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications;king-jien;2016 IEEE 66th Electronic Components and Technology Conference,0

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1. Vertical Stacking of Heterogeneous Chiplets of Duplexer on LNA/SOI;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05