Overview of 3D NAND Flash and progress of vertical gate (VG) architecture-Reference-Cited by-同舟云学术

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Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Published:2012-10 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology
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Author:

Lue Hang-Ting,Chen Shih-Hung,Shih Yen-Hao,Hsieh Kuang-Yeu,Lu Chih-Yuan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6459619/6466666/06466681.pdf?arnumber=6466681

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Influence of rapid thermal annealing on the wafer warpage in 3D NAND flash memory;Semiconductor Science and Technology;2019-01-22

3. Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory;Japanese Journal of Applied Physics;2018-03-23

4. Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation;Solid-State Electronics;2018-02

5. Scatterometry for advanced process control in semiconductor device manufacturing;Fifth International Conference on Optical and Photonics Engineering;2017-06-13

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