Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation-Reference-Cited by-同舟云学术

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Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

Published:2018-02 Issue: Volume:140 Page:46-50
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Kim Do-Bin,Kwon Dae Woong,Kim Seunghyun,Lee Sang-Ho,Park Byung-Gook

Funder

Ministry of Science, ICT and Future Planning

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. Katsumata R et al. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices. In: Proc symp VLSI technol; June 2009. p. 136–137.

2. Jang J et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory. In: Proc symp VLSI technol; June 2009. p. 192–193.

3. Lue H-T et al. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. In: Proc symp VLSI technol; June 2010. p. 131–132.

4. Three-dimensional NAND flash architecture design based on single-crystalline stacked array;Kim;IEEE Trans Electron Devices,2012

5. Lue H-T, Chen S-H, Shih Y-H, Hsieh K-Y, Lu C-Y. Overview of 3D NAND flash and progress of vertical gate (VG) architecture. In: Proc IEEE 11th int conf solid-state integr circuit technol (ICSICT); Oct/Nov 2012. p. 1–4.

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