Author:
Celano U.,Lee Y.,Serron J.,Smith C.,Franco J.,Ryu K.,Kim M.,Park S.,Lee J.,Kim J.,van der Heide P.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference11 articles.
1. High- k Gate Dielectrics;Houssa,2003
2. Lue, H.-T.; Chen, S.-H.; Shih, Y.-H.; Hsieh, K.-Y.; Lu, C.-Y. Overview of 3D NAND Flash and Progress of Vertical Gate (VG) Architecture. 2012 IEEE 11th Int. Conf. Solid-State Integr. Circuit Technol. 2012, 1–4. https://doi.org/10.1109/ICSICT.2012.6466681.
3. Three-Dimensional 128Gb MLC Vertical NAND Flash-Memory with 24-WL Stacked Layers and 50MB/s High-Speed Programming;Park;International Solid-State Circuits Conference,2014
4. Charge writing and detection by EFM and KPFM scanning probe techniques;Knorr;Microsc Anal,2012
5. Quantitative evaluation of local charge trapping in dielectric stacked gate structures using Kelvin probe force microscopy;Lubarsky;J Vac Sci Technol B Microelectron Nanom Struct,2002
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献