An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory-Reference-Cited by-同舟云学术

An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Junsen He¹,Yoon Dong-Hyun¹,Kim Tony Tae-Hyoung¹

Affiliation:

1. School of Electrical and Electronic Engineering, Nanyang Technological University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181848.pdf?arnumber=10181848

Reference13 articles.

1. 22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

2. 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

3. An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits;yi;2012 International SoC Design Conference (ISOCC),0

4. Energy Efficient 5Gb/s/pin Baseband Transceiver for 3D Memory Interface

5. Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

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