22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

Author:

Lee Dong Uk,Cho Ho Sung,Kim Jihwan,Ku Young Jun,Oh Sangmuk,Dae Kim Chul,Kim Hyun Woo,Lee Woo Young,Kim Tae Kyun,Yun Tae Sik,Kim Min Jeong,Lim SeungGyeon,Lee Seong Hee,Yun Byung Kuk,Moon Jun Il,Park Ji Hwan,Choi Seokwoo,Park Young Jun,Lee Chang Kwon,Jeong Chunseok,Lee Jae-Seung,Lee Sang Hun,We Woo Sung,Yun Jong Chan,Lee Doobock,Shin Junghyun,Kim Seungchan,Lee Junghwan,Choi Jiho,Ju Yucheon,Park Myeong-Jae,Lee Kang Seol,Hur Youngdo,Shim Daeyong,Lee Sangkwon,Chun Junhyun,Jin Kyo-Won

Publisher

IEEE

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1. Room-Temperature Hybrid Bonding of Via-middle TSV Wafer Fabricated by Direct Si/Cu Grinding and Residual Metal Removal;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Present and Future, Challenges of High Bandwith Memory (HBM);2024 IEEE International Memory Workshop (IMW);2024-05-12

3. MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

4. A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM;Micromachines;2024-04-23

5. A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection;IEEE Journal of Solid-State Circuits;2024-01

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