Room-Temperature Hybrid Bonding of Via-middle TSV Wafer Fabricated by Direct Si/Cu Grinding and Residual Metal Removal
Author:
Affiliation:
1. National Institute of Advanced Industrial Science and Technology (AIST),Tsukuba, Ibaraki,Japan
2. Okamoto Machine Tool Works, Ltd.,Annaka, Gunma,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10564841/10564831/10565051.pdf?arnumber=10565051
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1. Neuromorphic vision chip fabricated using three-dimensional integration technology
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4. 4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM
5. 22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST
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