TSPC Trigger-Based Testing Scheme for Pre-Bond Testing and Diagnosis of TSVs-Reference-Cited by-同舟云学术

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TSPC Trigger-Based Testing Scheme for Pre-Bond Testing and Diagnosis of TSVs

Published:2023-12-29 Issue: Volume: Page:11-17
ISSN:
Container-title:2023 2nd International Conference on Sensing, Measurement, Communication and Internet of Things Technologies (SMC-IoT)
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Author:

Yu Yang¹,Su Jingqiao¹,Xu Hongshui¹,Xiao Ziwen¹

Affiliation:

1. Harbin Institute of Technology,School of Electrical Engineering and Automation,Harbin,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10538468/10538519/10538604.pdf?arnumber=10538604

Reference13 articles.

1. Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects

2. Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

3. TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's

4. An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory

5. Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays

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