Impact of interconnects enhancement on SRAM design beyond 5nm technology node
Author:
Affiliation:
1. imec,Leuven,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181556.pdf?arnumber=10181556
Reference27 articles.
1. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a SRAM cell size;natarajan;IEDM,2014
2. The impact of assist-circuit design for 22nm SRAM and beyond
3. 17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization
4. A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications
5. 12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications
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1. A 4.24-GHz 128×256 SRAM Operating Double Pump Read Write Same Cycle in 5-nm Technology;IEEE Solid-State Circuits Letters;2024
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