A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications

Author:

Song Taejoong,Rim Woojin,Jung Jonghoon,Yang Giyong,Park Jaeho,Park Sunghyun,Kim Yongho,Baek Kang-Hyun,Baek Sanghoon,Oh Sang-Kyu,Jung Jinsuk,Kim Sungbong,Kim Gyuhong,Kim Jintae,Lee Youngkeun,Sim Sang-Pil,Yoon Jong Shik,Choi Kyu-Myung,Won Hyosig,Park Jaehong

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 49 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Tartan: Microarchitecting a Robotic Processor;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Design and Tool Solutions for Monolithic Three-Dimensional Integrated Circuits;Handbook of Computer Architecture;2024

4. Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

5. On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond;Microelectronics Journal;2023-08

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