A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM-Reference-Cited by-同舟云学术

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A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Zhou Yongliang¹,Yang Zhen¹,Wei Yiming¹,Lin Xiao¹,Wu Saiai¹,Lu Wenjuan¹,Peng Chunyu¹,Li Xin¹,Wu Xiulong¹

Affiliation:

1. Anhui University,School of Integrated Circuits,HeFei,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558668.pdf?arnumber=10558668

Reference21 articles.

1. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

2. A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation

3. Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

4. Design and Implementation of FinFET 12-T SRAM cell for low power Applications

5. Low Power 8T SRAM with High Stability and Bit Interleaving Capability

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