Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Author:

Wen Liang,Cheng Xu,Zhou Keji,Tian Shudong,Zeng Xiaoyang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Ultra8T: A sub-threshold 8T SRAM with leakage detection;Integration;2024-09

2. A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology;AEU - International Journal of Electronics and Communications;2024-04

4. Efficient and High Performance Ternary SRAM;2023 International Conference on Research Methodologies in Knowledge Management, Artificial Intelligence and Telecommunication Engineering (RMKMATE);2023-11-01

5. A single ended, single port configuration based 9 T SRAM cell for stability enhancement;Physica Scripta;2023-10-23

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