A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory-Reference-Cited by-同舟云学术

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A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory

Published:2014-11 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Athmanathan Aravinthan,Stanisavljevic Milos,Cheon Junho,Kang Seokjoon,Ahn Changyong,Yoon Junghyuk,Shin Minchul,Kim Taekseung,Papandreou Nikolaos,Pozidis Haris,Eleftheriou Evangelos

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6996072/7008838/07008879.pdf?arnumber=7008879

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network Accelerators;IEEE Transactions on Computers;2024-09

2. DynaPAT;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30

3. Temperature activated conductivity of Ge2Sb2Te5: connection to the variation of Fermi level and implications on resistance drift;Journal of Physics D: Applied Physics;2021-05-25

4. Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads;IEEE Design & Test;2021-02

5. Nonvolatile Multistates Memories for High-Density Data Storage;ACS Applied Materials & Interfaces;2020-08-19

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