A Comprehensive Review on FinFET, Gate All Around, Tunnel FET: Concept, Performance and Challenges
Author:
Affiliation:
1. Jaypee Institute of Information Technology, Noida,Department of Electronics & Communication Engineering,Noida (UP),India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009017/10009021/10009504.pdf?arnumber=10009504
Reference34 articles.
1. Impact of the vertical SOI 'DELTA' structure on planar device technology
2. Recent Trends in Novel Semiconductor Devices
3. Tunnel FET Based SRAM Cells – A Comparative Review
4. Effect of Gate Bias on Graphene Channel of G4-FET and Gate-All-Around MOSFET
5. Comparative analysis of junctionless bulk and SOI/SON FinFET
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