Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications

Author:

Nicosia Gianluca1,Righetti Niccolò1,Dong Yingda1

Affiliation:

1. NAND Technology Development, Micron Technology, Inc. Boise,ID,USA,83716

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Overcome the End of Life of 3D Flash Memory by Recovery Annealing, Aiming for Carbon Neutrality in Semiconductor Manufacturing;2024 IEEE International Memory Workshop (IMW);2024-05-12

2. Comprehensive physics-based modeling of post-cycling long-term data retention in 176L 3-D NAND Flash Memories;2024 IEEE International Memory Workshop (IMW);2024-05-12

3. Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

4. Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

5. Cycling Condition Impacts on 3D QLC NAND Reliability;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

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