Survey of low power testing of VLSI circuits-Reference-Cited by-同舟云学术

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Survey of low power testing of VLSI circuits

Published:2012-01 Issue: Volume: Page:
ISSN:
Container-title:2012 International Conference on Computer Communication and Informatics
language:
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Author:

Basker P.,Arulmurugan A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6151888/6158648/06158884.pdf?arnumber=6158884

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A low-power True Single Phase Clock scan cell design for VLSI testing;Materials Today: Proceedings;2021

2. Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods;Journal of Electronic Testing;2020-10

3. A Performance Comparison of Fuzzy Logic Based Truly Random Number Generator with Other Low Power LFSR Architectures;International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018;2018-12-21

4. Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing;Measurement and Control;2018-07-02

5. A Parallel Test Application Method towards Power Reduction;Journal of Electronic Testing;2017-03-25

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