Author:
Arulmurgan A.,Roobiha V.R.,Narendran G.,Praneshkumar K.,Gokul C.
Reference13 articles.
1. VLSI Test Principles and Architectures: Design for Testability;Wang,2006
2. P. Girard, Survey of low-power testing of VLSI circuits, IEEE Design & test of computers, pp. 82-92, 2002.
3. P. Basker, A. Arulmurugan, Survey of low power testing of VLSI circuits, 2012 International Conference on Computer Communication and Informatics, IEEE2012, pp. 1-7.
4. Temperature and voltage droop-aware test scheduling during scan shift operation;Lee;IEICE Electron. Exp.,2016
5. J.-F. Lin, M.-H. Sheu, Y.-T. Hwang, C.-S. Wong, M.-Y. Tsai, Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes, IEEE transactions on very large scale integration (vlsi) systems, pp.3033-3044,2017.
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