A circuit technique for leakage power reduction in CMOS VLSI circuits

Author:

Nandyala Venkata Ramakrishna,Mahapatra Kamala Kanta

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Key factors in the physical design of high-performance chips;SCIENTIA SINICA Informationis;2024-01-01

2. A 10-MHz CMOS-based Ring Oscillator with Low Power consumption For On-chip IC Applications;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12

3. A Hybrid Approach to Automated Power and IR drop reduction and Classification using Support Vector Machines;2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon);2022-11-20

4. Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits;2022 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS);2022-11-04

5. Comparative Analysis of Different Types of Inverters for Low Power at 45nm;2021 3rd International Conference on Advances in Computing, Communication Control and Networking (ICAC3N);2021-12-17

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