Key factors in the physical design of high-performance chips

Author:

FAN Lingyan,HUANG Cankun,ZHU Zhiwei,LIU Hailuan,MA Xiangyuan

Publisher

Science China Press., Co. Ltd.

Subject

Engineering (miscellaneous),General Computer Science

Reference17 articles.

1. K S, Y S, A S V. Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits. VLSICS, 2013, 4: 77-88.

2. Nandyala V R, Mahapatra K K. A circuit technique for leakage power reduction in CMOS VLSI circuits. In: Proceedings of International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016.

3. Bhatangar R. How PVT sensor IP and in-silicon monitoring enhance chip design. 2023. https://www.synopsys.com/blogs/chip-design/synopsys-tapes-out-slm-pvt-monitor-ip-on-tsmc-n5-n3e1.html.

4. Jain P. How chip floorplan design automation accelerates chip design. 2023. https://www.synopsys.com/blogs/chip-design/chip-floorplan-design-automation.html.

5. Mirhoseini A, Goldie A, Yazgan M, et al. Chip placement with deep reinforcement learning. 2020,.

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