The VMM3a ASIC
Author:
Affiliation:
1. DG Circuits, Syosset, NY, USA
2. Brookhaven National Laboratory, Upton, NY, USA
3. Horia Hulubei National Institute for Research and Development in Physics and Nuclear Engineering, Bucharest, Romania
Funder
U.S. Department of Energy, Office of Science, High Energy Physics
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics
Link
https://ieeexplore.ieee.org/ielam/23/9758990/9724214-aam.pdf
Reference19 articles.
1. A CMOS baseline holder (BLH) for readout ASICs
2. Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration
3. Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration
4. Amplitude and time measurement ASIC with analog derandomization: first results
5. Readout ASIC for 3D position-sensitive detectors
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