A SEB Hardened Trench Gate DMOS with HfO2 Gate Dielectric and Decelerating Electric Field Layer in Parasitic NPN Base
Author:
Affiliation:
1. University of Electronic Science and Technology of China,State Key Laboratory of Electronic Thin Films and Integrated Devices,Chengdu,China,610054
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10147163/10147396/10147721.pdf?arnumber=10147721
Reference14 articles.
1. SEB Hardened Power MOSFETs With High-K Dielectrics
2. Improved single-event hardness of trench power MOSFET with a widened split gate
3. Single-event burnout mechanisms in SiC power MOS-FE Ts;arthur;IEEE Trans NS,2018
4. Single-Event Effect Hardened VDMOS Device with Hole Bypass Structure
5. Single-Event Burnout Hardening 4H-SiC UMOSFET Structure
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1. TCAD Analysis of Single-Event Burnout Hardness for an Improved CoolSiC Trench MOSFET;IEEE Transactions on Electron Devices;2024-08
2. A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process;IEEE Transactions on Device and Materials Reliability;2024-03
3. Experimental Investigation and Hardening of Single-Event Gate Rupture in 100-V Spl-Gate Trench VDMOS;IEEE Transactions on Nuclear Science;2024-01
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