Bayesian Optimization of Large Glass Package Architecture for System-Level Reliability in High-Performance Computing Applications-Reference-Cited by-同舟云学术

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Bayesian Optimization of Large Glass Package Architecture for System-Level Reliability in High-Performance Computing Applications

Published:2024-05-28 Issue: Volume: Page:246-253
ISSN:
Container-title:2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
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Author:

Surillo Emanuel Torres¹,Sosa Ramón A.¹,Molina Christian¹,Park Hyunggyu²,Nimbalkar Pratik²,Srirangan Sriram³,Dahal Lila D.⁴,Lee Yongwon¹,Smet Vanessa¹

Affiliation:

1. Georgia Tech,Woodruff School of Mechanical Engineering,Atlanta,Georgia

2. Georgia Tech,3D Systems Packaging Research Center,Atlanta,Georgia

3. Georgia Tech,Atlanta,Georgia

4. Georgia Tech,Institute for Electronics and Nanotechnology,Atlanta,Georgia

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10564841/10564831/10564862.pdf?arnumber=10564862

Reference9 articles.

1. The next frontier: Enabling Moore’s Law using heterogeneous integration;Swaminathan;Chip Scale Review,2022

2. Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS® technology

3. Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect

4. InFO (Wafer Level Integrated Fan-Out) Technology

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Study of Chip-Package Interaction with All-Copper Interconnections on Advanced Glass Substrates;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

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