Author:
Phyu Myint Wai,Fu Kangkang,Goh Wang Ling,Yeo Kiat-Seng
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
29 articles.
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1. Low power low voltage TSPC FLIP-FLOP design;AIP Conference Proceedings;2024
2. Review of Dual-Edge Triggered Low-Power D Flip-Flops;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29
3. A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits;Engineering Research Express;2023-08-24
4. Comparative Analysis of Dual-edge Triggered and Sense Amplifier Based Flip-flops in 32 nm CMOS Regime;2023 International Conference in Advances in Power, Signal, and Information Technology (APSIT);2023-06-09
5. Performance Evaluation of Pulse Triggered Flip-Flops in 32 nm CMOS Regime;2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC);2023-05-04