A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits

Author:

Shah Owais AhmadORCID,Nijhawan Geeta,Khan Imran Ahmed

Abstract

Abstract In this work, a sense amplifier based flip flop (SAFF) is presented appropriate for high speed, high data activity and low power operations. The delay and power of the proposed flip flop have been considerably reduced as it uses a novel single-ended latch structure. The flip flop (FF) also achieves glitch free operation and can be operated and is functional at near-threshold voltage levels. SPICE simulations were carried out to do a comprehensive and quantifiable analysis between the presented architecture and formerly known architectures in 32 nm CMOS technology. The proposed design achieved a reduction of minimum 22.67% in power at nominal voltage. In terms of Power Delay Product (PDP), a reduction of 63.51% was observed. At 100 MHz clock frequency, the power dissipation was lowered by 30%. The proposed design at data activity of 100% consumes 28.24% less power whereas at activities of less than 12.5% it does not show significant improvements. However, the proposed design has an advantage in terms of speed and is 40% to 82% faster at nominal conditions and can also operate at wide supply voltage. It also has the second lowest transistor count and second lowest area. The power performance is verified by implementing the proposed design as a 4-bit shift register.

Publisher

IOP Publishing

Subject

General Engineering

Reference23 articles.

1. An efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks;Pasandi;IEEE Trans. Appl. Supercond.,2020

2. A low-power high-speed sense-amplifier-based flip-flop in 55 nm MTCMOS;You;Electronics,2020

3. Improved sense amplifier based flip flop design For Low power and high data activity circuits;Shah;Journal of Applied Science and Engineering,2022

4. Energy and area efficient spin–orbit torque nonvolatile flip-flop for power gating architecture;Ali;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2018

5. Performance analysis of an ultralow power circuit using single halo CNTFETs;Wang;Semicond. Sci. Technol.,2015

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Simplifying complex digital sequential circuit by an innovative mixed-signal circuit alternative;Computers and Electrical Engineering;2024-04

2. Enhancing Concrete Properties Through the Integration of Recycled Coarse Aggregate: A Machine Learning Approach for Sustainable Construction;2024 4th International Conference on Innovative Practices in Technology and Management (ICIPTM);2024-02-21

3. Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET;2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE);2023-11-23

4. Advancements in Binary Number Processing: Analyzing a CNTFET-Based Digital Circuit for 3-Bit Up and Down Counting with Challenges in Artificial Intelligence;2023 International Conference on Sustainable Communication Networks and Application (ICSCNA);2023-11-15

5. High Performance Design of Single Edge Triggered Johnson Counter;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3