Comparative Analysis of Dual-edge Triggered and Sense Amplifier Based Flip-flops in 32 nm CMOS Regime-Reference-Cited by-同舟云学术

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Comparative Analysis of Dual-edge Triggered and Sense Amplifier Based Flip-flops in 32 nm CMOS Regime

Published:2023-06-09 Issue: Volume: Page:
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Container-title:2023 International Conference in Advances in Power, Signal, and Information Technology (APSIT)
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Author:

Shah Owais Ahmad¹,Bansal Shivangi¹,Mavi Prashant Kumar²,Yadav Anupam¹,Vats Satvik³,Ishrat Zaiba²

Affiliation:

1. Noida International University,Department of Electronics & Communication Engineering,Gautam Budh Nagar,India

2. IIMT College of Engineering,Department of Electronics & Communication Engineering,Greater Noida,India

3. Graphic Era Hill University,Department of Computer Science & Engineering,Dehradun,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10201653/10201654/10201721.pdf?arnumber=10201721

Reference15 articles.

1. Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop

2. New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements

3. Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation

4. A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

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