Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop
Author:
Affiliation:
1. VIRTUS – IC Design Centre of ExcellenceSchool of Electrical and Electronic Engineering, Nanyang Technological UniversitySingaporeSingapore
Funder
Economic Development Board - Singapore
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2018.1134
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3. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
4. A 200 MHz 13 mm2 2‐D DCT macrocell using sense‐amplifying pipeline flip‐flop scheme;Matsui M.;J. Solid‐State Circuits,1994
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