A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Author:

Chiu Geng-Ming,Li James Chien-Mo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 41 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On Evaluating Test Response Obfuscation and Encryption Countermeasures;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03

2. SASL-JTAG: A Light-Weight Dependable JTAG;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

3. A Survey of Chips Security Technology Based on Scan Chain;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

4. A Low-overhead PUF-based Secure Scan Design;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

5. Power Analysis Attack on Locking SIB based IJTAG Achitecture;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

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