A Survey of Chips Security Technology Based on Scan Chain
Author:
Affiliation:
1. National and Local Jiont Engineering, College of Integrated Circuit Secience and Engineering, Nanjing University of Posts and Telecommunications,Laboratory of RF Intergration and Micro-assembly Technology,Nanjing,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10218344/10218369/10218659.pdf?arnumber=10218659
Reference40 articles.
1. Self-Test Techniques for Crypto-Devices
2. PUF-based secure test wrapper design for cryptographic SoC testing
3. A novel differential scan attack on advanced DFT structures
4. Attacks and Defenses for JTAG
5. Design and implementation of key isolation secure scan chain circuit(in Chinese);chen;J Nanjing Univ Posts Telecommun,2017
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