Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme-Reference-Cited by-同舟云学术

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Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Published:2012-02 Issue:2 Volume:20 Page:361-366
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Hwang Yin-Tsung,Lin Jin-Fa,Sheu Ming-Hwa

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6129939/05682078.pdf?arnumber=5682078

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5. A Conditional Feedthrough Pulsed Flip-Flop using MTCMOS Technique;2023 4th International Conference for Emerging Technology (INCET);2023-05-26

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