A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-<i>V</i> <sub>DD</sub> Assist and Bitline Leakage Compensation-Reference-Cited by-同舟云学术

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V _DD Assist and Bitline Leakage Compensation

Published:2023-05 Issue:5 Volume:31 Page:684-695
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Wang Yuqi¹^ORCID,Zhang Shen¹,Li Yifei¹^ORCID,Chen Jian¹^ORCID,Zhao Wenfeng²^ORCID,Ha Yajun³^ORCID

Affiliation:

1. Reconfigurable and Intelligent Computing Laboratory (RICL), School of Information Science and Technology, ShanghaiTech University, Shanghai, China

2. Department of Electrical and Computer Engineering, Binghamton University, State University of New York (SUNY), Binghamton, NY, USA

3. School of Information Science and Technology and the Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, ShanghaiTech University, Shanghai, China

Funder

National Natural Science Foundation of China

Zhangjiang Laboratory

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10106533/10043640.pdf?arnumber=10043640

Reference28 articles.

1. Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing

2. Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security

3. A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory;jeloka;IEEE J Solid-State Circuits,2016

4. Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping

5. A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

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