A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory
Author:
Affiliation:
1. Hefei University of Technology,School of Electronic Science,China,230601
2. Shanghai Jiao Tong University,School of Electronic Information and Electrical Engineering,Shanghai,China,200240
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558593.pdf?arnumber=10558593
Reference13 articles.
1. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
2. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
3. A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
4. A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
5. Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs
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