NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact-Reference-Cited by-同舟云学术

NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact

Published:2023-02 Issue:2 Volume:31 Page:163-176
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Taehak¹^ORCID,Jeong Jaehoon¹^ORCID,Woo Seungmin²,Yang Jeonggyu¹^ORCID,Kim Hyunwoo²,Nam Ahyeon²,Lee Changdong²,Seo Jinmin²,Kim Minji²,Ryu Siwon²,Oh Yoonju²^ORCID,Song Taigon¹^ORCID

Affiliation:

1. School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea

2. School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea

Funder

National Research and Development Program through the National Research Foundation of Korea

Ministry of Science and ICT, South Korea

Basic Science Research Program through the National Research Foundation of Korea

Ministry of Education

BK21 FOUR Project

Ministry of Education, Korea

Samsung Electronics Company Ltd

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10019332/09997505.pdf?arnumber=9997505

Reference64 articles.

1. Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries

2. High-Performance Stacked Double-Layer N-Channel Poly-Si Nanosheet Multigate Thin-Film Transistors

3. Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors

4. Vertically-stacked silicon nanosheet field effect transistors at 3 nm technology nodes;dash;Proc Devices Integr Circuit (DevIC),2019

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