Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations
Author:
Affiliation:
1. Kookmin University,School of Electrical Engineering,Seoul,Rep. of Korea
Funder
National Research Foundation of Korea
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10528356/10528364/10528728.pdf?arnumber=10528728
Reference11 articles.
1. Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology
2. NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact
3. PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes
4. Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
5. Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization
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