A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector
Author:
Affiliation:
1. University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI and IME/FST-ECE,Macao,China
2. Institute of Semiconductors, Chinese Academy of Sciences,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9933920/9934110/09934542.pdf?arnumber=9934542
Reference50 articles.
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4. A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
5. A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS
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